1. Field of the Invention
This invention relates to a multilayer semiconductor device and, in particular, to a multilayer semiconductor device that is suitably used as electronic parts composing an electronic device such as an IC card. Also, this invention relates to a method of manufacturing the multilayer semiconductor device.
2. Description of the Related Art
Generally, an electronic device operates with plural semiconductor parts (electronic parts) being mounted on one surface or both surfaces of a printed-wiring board. The plural semiconductor parts are each disposed usually in parallel lengthwise and crosswise on the surface of the printed-wiring board.
In recent years, a multilayer (or multilayer-type) semiconductor device is developed as the electronic device in order to respond to the high-density mounting of the parts. The multilayer semiconductor device comprises plural semiconductor chips or plural semiconductor devices being laminated together in a single semiconductor device (or semiconductor package).
The above-mentioned multilayer semiconductor device is manufactured such that semiconductor devices having a printed-wiring board for BGA (ball grid array) are each fabricated, and then the devices thus fabricated are laminated together on a circuit board (a motherboard) for mounting a semiconductor device.
A multilayer semiconductor device is known that comprises plural wiring boards with a semiconductor chip mounted thereon and sealed by a sealing resin, interlayer connecting terminals for connecting neighboring two of the wiring boards, and plural dummy bumps disposed mutually in parallel with a certain distance on the mounting side of the interlayer connecting terminal (e.g., JP-A-2003-133519).
Also, a multilayer semiconductor device is known that comprises plural intermediate boards with a semiconductor chip mounted thereon, interlayer connecting terminals for connecting neighboring two of the intermediate boards, and external connecting terminals made from a material softer than the interlayer connecting terminal (e.g., JP-A-2002-76265).
By the way, the above-mentioned conventional multilayer semiconductor devices are manufactured such that laminated semiconductor devices (BGA type semiconductor devices) to be bonded each other are conveyed into a reflow furnace heated to above a solder melting point by means of a conveyer and the like, and then the semiconductor devices with a solder ball melted in the reflow furnace are taken out from the reflow furnace to harden the solder ball.
However, the multilayer semiconductor device of JP-A-2003-133519 has the next problems.
The multilayer semiconductor device comprises the dummy bumps interposed between the neighboring two wiring boards. The dummy bump allows the bend of the semiconductor chips when a heat cycle test and a mechanical stress test are performed. However, the dummy bump does not have a function to restrict inclination of the semiconductor device (the wiring board). This may cause a problem as described below.
In the multilayer semiconductor device of JP-A-2003-133519, when a reflow mounting process is conducted with a solder ball faced downward, the stacking (upper) semiconductor device is connected by being soldered to a land preliminarily formed on the lower semiconductor device. When the reflow mounting process is conducted with the solder ball faced upward vice versa, the stacked (lower) semiconductor device is connected by being soldered to a land preliminarily formed on the upper semiconductor device.
In this case, when the semiconductor device is conveyed into the reflow furnace by the conveyer, the semiconductor device is heated gradually in the reflow furnace, so that the solder ball starts to melt at above the solder melting point. The solder ball does not melt simultaneously at all of the mounting positions thereof. The solder ball passed through the reflow furnace early reaches the solder melting point early. Thus, the early passed solder ball starts to melt early.
The solder ball thus melted changes in shape while being wetted and spread on the land, and decreases in height. In this case, due to difference in timing when the solder ball starts to melt as mentioned above, difference in height is caused between the solder ball spread over the land and the solder ball not spread over the land yet. For this reason, the semiconductor device inclines to form a slope. According as the inclination of the semiconductor device increases (the inclination being likely accelerated by the own weight of the device depending on the melting timing), positional relationship between the solder ball and the land changes, although they were in even contact with each other before the reflow mounting process. Therefore, distance between a solder ball starting to melt late and the corresponding land becomes greater than that between the solder ball starting to melt early and the corresponding land, so that parallelization degree between the wiring boards deteriorates. This causes a failure in interlayer connection to reduce the reliability of interlayer connection. The more the number of the laminated semiconductor devices increases, the more the failure becomes remarkable because the whole weight is increased.
On the other hand, the device of JP-A-2002-76265 is less likely to cause the problem as raised in JP-A-2003-133519 because the solder ball is less likely to decrease in height even after the solder ball is spread over the land in the reflow mounting process. However, another problem is raised that the manufacturing cost must be increased because the solder ball is formed of a particular ball with a core made from copper or nickel.